The present invention relates to an improvement of a digital data play back apparatus and a method for playing back digital data which is optically, magnetically or optomagnetically recorded on a recording medium such as, for example, a disc or the like.
As is already known, a play back signal processing system in a recording apparatus for optically, magnetically or optomagnetically recording data pattern is generally constituted to obtain play back data by amplifying the play back signal read with a play back head from the recording medium and further equalizing a waveform of the play back signal with a waveform equalizer followed by inputting the play back signal to a data detection device to identify data and decoding the signal to obtain reproduction data.
That is, a distortion generated as a result of the passage of data through the recording channel is corrected with the waveform equalizer and a signal error detection ratio is suppressed within an allowance scope with the result that a peak position of the waveform is determined and a zero cross point is determined through differentiation. In the PRML (Partial Response Maximum Likelihood) signal processing method in recent years, a method is used which detects data as a sequence by making use of a correlation before and after the signal.
Here, in order to detect data, an interval in which data is recorded, namely, a channel clock frequency, and phase information thereof are required. This channel clock is recovered (restored) by using a PLL (Phase Locked Loop) from the played back signal.
In the data recorded on the recording medium, there is present at the initial portion of data a VFO region in which a signal is recorded in a single data repetition pattern repeated by integer times of the clock for recording data for timing recovery. The peak position of the VFO signal after the waveform equalization, and the position at which the signal crosses a specific threshold value are detected, and the channel clock is recovered thereby enabling synchronization to the frequency and phase of the recorded data.
The following data is detected by using this synchronized clock. However, because of the change in the rotational speed of discs or the like, the phase at the initial portion of data does not agree with the phase at the end portion of the data. Then, even during the play back of the data, the phase shift between the data detection timing and the play back clock by the PLL is feed back to the PLL thereby allowing the phase drift at the data portion to follow the clock.
Since the VFO region has a signal of a single frequency, a high quality phase signal can be obtained. However, since the data portion has a complicated waveform, the position at which the phase error can be detected is small, the quality thereof is lowered under the influence of the waveform interference. In the VFO region, the PLL is normally referred to as the “Acquisition mode” wherein the frequency is acquired at a high speed to follow the phase. However, in the data region, the PLL moves to the “trace mode” which is an operation in which the loop gain of the PLL is suppressed to a low level. In this trace mode, a mild frequency change like a rotational drifts can be followed, but a rapid change in bit unit by noises, waveform interference or the like cannot be followed.
In the PRML signal processing method, there are many cases in which the play back signal is quantized at a discrete time by using an A/D (Analogue/Digital) converter prior to the inputting of the play back signal to the waveform equalizer. In the sampling clock given to the A/D converter, the channel clock is used which is recovered by using the PLL.
FIGS. 1A through 1H are views showing a signal of an optical disc apparatus in the case where the play back signal is not sampled in a discrete time as used many times in the PRML signal processing, but the threshold value is detected in a continuous time to detect data.
The user data to be recorded is a data row which is a random combination of 0 and 1. In order to record the data on the recording medium, the number of 0's between 1 and 1 as shown in FIG. 1A is modulated according to a run length limit (RLL) code. The data writing signal is converted into a signal (FIG. 1B) in which the ON and OFF of data (FIG. 1A) is toggled at the position of 1 in the case of mark edge recording. As a consequence, a mark (FIG. 1C) is recorded on the recording medium. The play back signal (FIG. 1D) in the case where this mark (FIG. 1C) is read is allowed to pass through a differential circuit so that a differential waveform (FIG. 1E) can be obtained. The peak of the differential waveform (FIG. 1E) corresponds to the position of 1 of the data which is modulated with the RLL code of the data (FIG. 1A).
The channel clock recovered in the PLL circuit by using the signal of the VFO region may assume the state shown in FIG. 1G. If so, this clock (FIG. 1G) can form the data detection window (FIG. 1F). If the detection window (FIG. 1F) has a differential-waveform peak of 1, the detection data (FIG. 1H) can be acquired by outputting “0. ” The detection data (FIG. 1H) is RLL code data. Hence, the user data recorded can be recovered by allowing the detection data (FIG. 1H) to pass through the decoding circuit.
In the case where the phase of the play back signal and the phase of the channel clock synchronize each other, the peak of the differential signal (FIG. 1E) is located in the center of the data detection window (FIG. 1F). Consequently, although it is easy to detect whether or not the peak is present in the data detection window (FIG. 1F), the peak of the differential signal (FIG. 1E) is shifted to the end of the data detection window (FIG. 1F) along with the shift of the phase, so that the peak ultimately enters into the adjacent window thereby generating a detection error.
Then, as shown in FIG. 2, the phase error between the peak position of the differential waveform and the channel clock is detected with the phase comparator. And the error is converted into a voltage value with a charge pump to control the voltage control oscillator (VCO) as a result of the conversion. As a consequence, the clock phases which are recovered with the play back signal and the PLL can be allowed to synchronize each other.
In such method, a detection error is likely to be generated when the mark edge is not raised with the time in the data detection window. When the recording density is heightened, the rise of the edge becomes mild under the influence of the frequency response characteristics of the recording medium. In order to correct the rise to more abrupt rise, it is required to amplify the high frequency component characteristic with a waveform equalizer. However, since the noise component in a high frequency area is also raised in this correction, the S/N is deteriorated. Thus, in this signal processing method, there is a limit in the heightening of the density.
One method of overcoming this problem is a PRML signal processing method. In the PRML, since the influence of the response waveform to a certain bit is allowed to be exerted upon the adjacent bit or a plurality of bits, data can be recorded in a high density without emphasizing the high frequency component of the response of signal processing channel.
Instead of this, the degree of influence upon a plurality of bits is required to be controlled to a value determined with the PR class. Since the degree of the mutual interference between bits is controlled, the waveform having a mild change which cannot be detected in the threshold value is optimally detected (an ML detection) in a sequence of waveforms so that data can be detected without errors.
FIGS. 3A through 3F are views showing how the data row (FIG. 3A) which is the same as FIG. 1A will be represented with in the PRML method. FIG. 3C is a view showing a bit row wherein the case in which the writing signal (FIG. 3B) for each channel clock is turned on is set to 1 while the case in which the signal is turned off is set to 0. Now, suppose that the PR class is (1, 2, 2, 1) as shown in FIG. 3D.
In this PR equalization, it is intended to show that a response waveform played back from the channel in the case where the writing bit is 1 will be as shown in FIG. 3D. As shown in FIG. 3E, the play back waveform corresponding to the writing bit row (FIG. 3C) is represented as a superposition of the response waveform of each bit, so that the waveform shown in FIG. 3F can be obtained.
Thus, in the case of the PR equalization, what is controlled with the PR equalizer and is used for the input of the ML detector is the amplitude value at the time of sampling. Consequently, in the PRML signal processing, the play-back signal is converted into an amplitude value system quantified at the discrete time for each channel clock with the A/D converter before the play back signal is input to the equalizer. After that the play back signal is processed with the digital circuit in almost all the cases.
In the PLL phase error detector used in the PRML signal processing system optical disc apparatus, an output signal of the equalizer is made discrete in the direction of time. Unlike the method explained by using FIGS. 1A through 1H, the data phase and the phase of the channel clock to be recovered with the PLL cannot be directly compared with each other. It is necessary to convert a shift in the sampled amplitude value into a phase error.
For example, U.S. Pat. No. 4,890,299 discloses a method for converting a shift in the amplitude value into a phase error and a structure thereof. A calculation is made as to what degree of timing phase gradient has either in the plus or minus direction from the current amplitude value, amplitude values before one or two samples, and an ideal equalization amplitude corresponding to the values.
However, what is disclosed here is a case in which an ideal value of the play back waveform after the PR equalization becomes three levels. When the recording density becomes high, the frequency response of the medium becomes relatively insufficient so that the PR class needs to be raised. However, since the points of samples in which waveforms mutually interferes with each other increases in these classes, the amplitude level increase after the equalization of the waveform with the result that the phase error cannot be detected in the method in which the three levels are assumed.
How many levels the waveform value is divided into after the PR equalization depends upon the PR class and the modulation method used. As in the examples of FIGS. 3A to 3F, the waveform value is divided into five level (0, 1, 3, 5 and 6) if the levels (1, 2, 2, 1) are used as the PR class and if PLL (2, 7), wherein the minimum number (d constraint) of 0s existing between “1” and “1” is limited to 2, is used as modulation method.
Even if the same PR class, i.e., the levels (1, 2, 2, 1) is used, the waveform value will be divided into seven levels (0, 1, 2, 3, 4, 5 and 6) in the case where the d constraint is 0 or the PLL (1, 7), wherein the d restriction is limited to 1, is used as modulation method. This holds true when the maximum number (k constraint) of 0s existing between “1” and “1” is 4 or more.
In this manner, in the case of the class in which the level of the waveform value after the PR equalization is 5 through 7, it is impossible to calculate the timing phase gradient from the amplitude value of the waveform in the method disclosed in U.S. Pat. No. 4,890,299.
Incidentally, with respect to this problem, as shown in Jpn. Pat. Appln. KOKAI Publication No. 2000-195191 filed by the same applicant of the present invention, a countermeasures technique is already filed which facilitates a phase synchronization between data and a block by detecting a timing phase gradient from the amplitude value sampled at a discrete time also in the PR class in which the amplitude value after equalization becomes 5 through 7 levels. However, in the current situation in which technical development is briskly made, there can be seen a tendency that a countermeasures having a different structure is also desired.